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#define | ATP_TPEN_ADC0 (0x01) |
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#define | ATP_TPEN_ADC1 (0x02) |
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#define | ATP_TPEN_AFE (0x03) |
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#define | ATP_TPEN_BIAS (0x04) |
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#define | ATP_TPEN_CP (0x07) |
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#define | ATP_TPEN_NONE (0x00) |
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#define | ATP_TPEN_TIMING (0x05) |
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#define | ATP_TPEN_TX (0x06) |
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#define | CPU_CTL_CPU_RST (0x40) |
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#define | CPU_CTL_FRZ_BRK_EN (0x10) |
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#define | CPU_CTL_HALT (0x01) |
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#define | CPU_CTL_ISTEP (0x04) |
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#define | CPU_CTL_RST_BRK_EN (0x20) |
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#define | CPU_CTL_RUN (0x02) |
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#define | CPU_CTL_SW_BRK_EN (0x08) |
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#define | CPU_ID_HI_DMEM_SIZE_BM (0x03FE) |
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#define | CPU_ID_HI_MPY (0x0001) |
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#define | CPU_ID_HI_PMEM_SIZE_BM (0xFC00) |
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#define | CPU_ID_LO_CHIP_ID_BM (0xFF00) |
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#define | CPU_ID_LO_CHIP_VERSION_BM (0x00FF) |
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#define | CPU_STAT_HALT_RUN (0x01) |
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#define | CPU_STAT_PUC_PND (0x04) |
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#define | CPU_STAT_SWBRK_PND (0x08) |
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#define | FCOUNT_STATUS_RESULT_RDY (0x0001) |
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#define | GPIO_PCFG_IEN (0x0001) |
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#define | GPIO_PCFG_IRQ_FLAG (0x0004) |
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#define | GPIO_PCFG_PU (0x0002) |
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#define | GPIO_PDIR_INPUT (0x00) |
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#define | GPIO_PDIR_OUTPUT (0x01) |
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#define | LPWKUP_CTRL_CLK_EN (0x0002) |
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#define | LPWKUP_CTRL_IEN (0x0001) |
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#define | LPWKUP_CTRL_RESET_N (0x0004) |
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#define | LPWKUP_STATUS_COUNT_SYNC (0x0004) |
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#define | LPWKUP_STATUS_CTRL_RDY (0x0002) |
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#define | LPWKUP_STATUS_PERIOD_RDY (0x0001) |
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#define | MEM_CTL_MEM_REG (0x04) |
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#define | MEM_CTL_RDWR (0x02) |
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#define | MEM_CTL_START (0x01) |
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#define | MEM_CTL_SW_BW (0x08) |
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#define | OTP_CTRL_OTP_EN (0x01) |
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#define | OTP_CTRL_PPROG (0x08) |
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#define | OTP_CTRL_PPROG_IO_EN (0x40) |
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#define | OTP_CTRL_PRD (0x02) |
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#define | OTP_CTRL_PTM_BM (0x30) |
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#define | OTP_CTRL_PWE (0x04) |
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#define | OTP_CTRL_VPP_RDY (0x80) |
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#define | PMUT_CAP_VAL_CONNECT (0x0040) |
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#define | PMUT_CAP_VAL_VALUE_BM (0x003F) |
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#define | PMUT_CHPUMP_CP_CLK_SEL (0x1000) |
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#define | PMUT_CHPUMP_HVVDD_CYCLES_BM (0x0007) |
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#define | PMUT_CHPUMP_HVVDD_FON (0x0200) |
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#define | PMUT_CHPUMP_RUN_CP_IN_RX (0x2000) |
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#define | PMUT_CHPUMP_SMCLK_DIV_1 (0x0000) |
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#define | PMUT_CHPUMP_SMCLK_DIV_2 (0x0010) |
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#define | PMUT_CHPUMP_SMCLK_DIV_4 (0x0020) |
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#define | PMUT_CHPUMP_SMCLK_DIV_8 (0x0030) |
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#define | PMUT_CHPUMP_SMCLK_DIV_BM (0x0030) |
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#define | PMUT_CLK_BIAS_0_MAX_FREQ (65938) |
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#define | PMUT_CLK_BIAS_1_MAX_FREQ (102500) |
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#define | PMUT_CLK_BIAS_2_MAX_FREQ (153125) |
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#define | PMUT_CLK_BIAS_3_MAX_FREQ (212500) |
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#define | PMUT_CLK_FREQ_TRIM_MAX_BIAS_0 (300) |
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#define | PMUT_CLK_FREQ_TRIM_MAX_BIAS_1 (400) |
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#define | PMUT_CONFIG_ADC_LF_EN (0x4000) |
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#define | PMUT_CONFIG_AFE_BIAS_EN (0x2000) |
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#define | PMUT_CONFIG_CIC_ODR_16 (0x0300) |
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#define | PMUT_CONFIG_CIC_ODR_2 (0x0600) |
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#define | PMUT_CONFIG_CIC_ODR_32 (0x0200) |
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#define | PMUT_CONFIG_CIC_ODR_4 (0x0500) |
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#define | PMUT_CONFIG_CIC_ODR_8 (0x0400) |
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#define | PMUT_CONFIG_CIC_ODR_BM (0x0700) |
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#define | PMUT_CONFIG_CP_ACTIVE_DISCHARGE (0x0004) |
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#define | PMUT_CONFIG_RX_PWR_OVERRIDE (0x1000) |
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#define | PMUT_CONFIG_SINGLE_ENDED_TX (0x0002) |
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#define | PMUT_CONFIG_TX0_ENABLE (0x0008) |
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#define | PMUT_CONFIG_TX1_ENABLE (0x0010) |
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#define | PMUT_CONFIG_TX2_ENABLE (0x0020) |
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#define | PMUT_CONFIG_TX3_ENABLE (0x0040) |
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#define | PMUT_CONFIG_VREF_CTRL (0x0001) |
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#define | PMUT_CTRL_ENABLE (0x0001) |
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#define | PMUT_CTRL_EOF_IEN (0x0004) |
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#define | PMUT_CTRL_ERROR_IEN (0x0008) |
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#define | PMUT_CTRL_RESET (0x0002) |
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#define | PMUT_STATUS_ACTIVE (0x0010) |
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#define | PMUT_STATUS_EOF_IFG (0x0004) |
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#define | PMUT_STATUS_ERROR_IFG (0x0008) |
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#define | PMUT_STATUS_RDY_CONFIG_WRITE (0x0040) |
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#define | PMUT_STATUS_RDY_NEXT_WR_PTR (0x0020) |
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#define | PT_CTRL_IEN (0x01) |
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#define | PT_CTRL_RST (0x02) |
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#define | PT_SELECT_SOURCE_BM (0x01) |
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#define | PT_SELECT_SOURCE_PIN_0 (0x00) |
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#define | PT_SELECT_SOURCE_PIN_1 (0x01) |
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#define | SCM_CPU_CLK_FREQ_TRIM_BM (0x3F) |
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#define | SCM_CPU_CLK_STANDBY (0x40) |
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#define | SCM_PASSWORD_VALUE (0x00A5) |
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#define | SCM_PMUT_CLK_BIAS_TRIM_BM (0xC000) |
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#define | SCM_PMUT_CLK_BIAS_TRIM_BS (14) |
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#define | SCM_PMUT_CLK_DIV_1 (0x0000) |
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#define | SCM_PMUT_CLK_DIV_2 (0x1000) |
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#define | SCM_PMUT_CLK_DIV_4 (0x2000) |
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#define | SCM_PMUT_CLK_DIV_8 (0x3000) |
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#define | SCM_PMUT_CLK_DIV_BM (0x3000) |
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#define | SCM_PMUT_CLK_EXT_EN (0x0800) |
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#define | SCM_PMUT_CLK_FREQ_TRIM_BM (0x01FF) |
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#define | SCM_PMUT_CLK_PAD_MODE_AT (0x0400) |
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#define | SCM_PMUT_CLK_PAD_MODE_BM (0x0600) |
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#define | SCM_PMUT_CLK_PAD_MODE_INPUT (0x0600) |
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#define | SCM_PMUT_CLK_PAD_MODE_NONE (0x0000) |
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#define | SCM_PMUT_CLK_PAD_MODE_PMUT (0x0200) |
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#define | SCM_RTC_CLK_EXT_EN (0x04) |
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#define | SCM_RTC_CLK_PAD_MODE_AT (0x02) |
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#define | SCM_RTC_CLK_PAD_MODE_BM (0x03) |
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#define | SCM_RTC_CLK_PAD_MODE_INPUT (0x03) |
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#define | SCM_RTC_CLK_PAD_MODE_NONE (0x00) |
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#define | SCM_RTC_CLK_PAD_MODE_RTC (0x01) |
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#define | SHASTA_ALGO_INFO_PTR_ADDR (SHASTA_CONFIG_PTR_ADDR + 2) |
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#define | SHASTA_CONFIG_PTR_ADDR SHASTA_DATA_MEM_ADDR |
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#define | SHASTA_CPU_ID_HI_VALUE (0x2041) |
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#define | SHASTA_CPU_ID_VALUE (0x2041) |
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#define | SHASTA_CPU_TRIM_DEFAULT (0x1E) |
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#define | SHASTA_CPU_TRIM_MAX (63) |
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#define | SHASTA_DATA_MEM_ADDR 0x1000 |
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#define | SHASTA_DATA_MEM_SIZE 0x1000 |
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#define | SHASTA_DBG_REG_CPU_CTL (0x04) |
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#define | SHASTA_DBG_REG_CPU_ID_HI (0x01) |
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#define | SHASTA_DBG_REG_CPU_ID_LO (0x00) |
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#define | SHASTA_DBG_REG_CPU_STAT (0x05) |
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#define | SHASTA_DBG_REG_MEM_ADDR (0x02) |
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#define | SHASTA_DBG_REG_MEM_CTL (0x06) |
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#define | SHASTA_DBG_REG_MEM_DATA (0x03) |
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#define | SHASTA_FCOUNT_CYCLES (128) |
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#define | SHASTA_LAST_16BIT_DBG_REG SHASTA_DBG_REG_MEM_DATA |
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#define | SHASTA_PMUT_TRIM_DEFAULT (0x4028) |
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#define | SHASTA_PROG_MEM_ADDR 0xE800 |
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#define | SHASTA_PROG_MEM_BASE_ADDR 0xE000 |
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#define | SHASTA_PROG_MEM_SIZE 0x1800 |
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#define | SHASTA_REG_ATP_TPEN (0x01C0) |
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#define | SHASTA_REG_ATP_TPSEL (0x01C1) |
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#define | SHASTA_REG_FCOUNT_CTRL (0x01D0) |
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#define | SHASTA_REG_FCOUNT_RESULT (0x01D2) |
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#define | SHASTA_REG_FCOUNT_STATUS (0x01D4) |
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#define | SHASTA_REG_GPIO_0_PCFG (0x01E0) |
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#define | SHASTA_REG_GPIO_0_PDIN (0x01E1) |
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#define | SHASTA_REG_GPIO_0_PDIR (0x01E3) |
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#define | SHASTA_REG_GPIO_0_PDOUT (0x01E2) |
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#define | SHASTA_REG_GPIO_1_PCFG (0x01E4) |
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#define | SHASTA_REG_GPIO_1_PDIN (0x01E5) |
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#define | SHASTA_REG_GPIO_1_PDIR (0x01E7) |
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#define | SHASTA_REG_GPIO_1_PDOUT (0x01E6) |
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#define | SHASTA_REG_LPWKUP_COUNT (0x0196) |
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#define | SHASTA_REG_LPWKUP_CTRL (0x0192) |
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#define | SHASTA_REG_LPWKUP_PERIOD (0x0190) |
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#define | SHASTA_REG_LPWKUP_STATUS (0x0194) |
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#define | SHASTA_REG_OTP_ADDR (0x01E8) |
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#define | SHASTA_REG_OTP_CTRL (0x01E9) |
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#define | SHASTA_REG_OTP_DATA (0x01EA) |
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#define | SHASTA_REG_PMUT_CAP_VAL (0x01AC) |
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#define | SHASTA_REG_PMUT_CHPUMP (0x01A2) |
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#define | SHASTA_REG_PMUT_CONFIG (0x01A0) |
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#define | SHASTA_REG_PMUT_CTRL (0x01A8) |
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#define | SHASTA_REG_PMUT_DMA_END_PTR (0x01B0) |
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#define | SHASTA_REG_PMUT_DMA_WRT_PTR (0x01AE) |
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#define | SHASTA_REG_PMUT_IP (0x01A6) |
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#define | SHASTA_REG_PMUT_NEXT_WRT_PTR (0x01AA) |
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#define | SHASTA_REG_PMUT_STATUS (0x01A4) |
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#define | SHASTA_REG_PT_CTRL (0x01D8) |
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#define | SHASTA_REG_PT_RESULT (0x01DA) |
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#define | SHASTA_REG_PT_SELECT (0x01D9) |
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#define | SHASTA_REG_SCM_CPU_CLK (0x01F3) |
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#define | SHASTA_REG_SCM_PASSWORD (0x01F4) |
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#define | SHASTA_REG_SCM_PMUT_CLK (0x01F0) |
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#define | SHASTA_REG_SCM_RTC_CLK (0x01F2) |
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#define | SHASTA_REG_SPI_CTRL (0x0204) |
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#define | SHASTA_REG_SPI_DMA_PTR (0x0206) |
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#define | SHASTA_REG_SPI_START_ADDR (0x0208) |
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#define | SHASTA_REG_SPI_WR_ADDR (0x0200) |
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#define | SHASTA_REG_SPI_WR_MASK (0x0202) |
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#define | SHASTA_REG_SYS_CTRL (0xA000) |
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#define | SHASTA_SMCLK_CYCLES_PER_PMUT (16) |
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#define | SPI_CMD_DATA_MEM (0x0000) |
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#define | SPI_CMD_DBG_REG_ACCESS (0x8000) |
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#define | SPI_CMD_DBG_REG_READ (SPI_CMD_DBG_REG_ACCESS | SPI_CMD_READ) |
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#define | SPI_CMD_DBG_REG_WRITE (SPI_CMD_DBG_REG_ACCESS | SPI_CMD_WRITE) |
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#define | SPI_CMD_MEM_ACCESS (0x0000) |
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#define | SPI_CMD_MEM_READ (SPI_CMD_MEM_ACCESS | SPI_CMD_READ) |
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#define | SPI_CMD_MEM_WRITE (SPI_CMD_MEM_ACCESS | SPI_CMD_WRITE) |
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#define | SPI_CMD_PROG_MEM (0x2000) |
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#define | SPI_CMD_READ (0x0000) |
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#define | SPI_CMD_SYS_CTRL_ACCESS (0xA000) |
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#define | SPI_CMD_SYS_CTRL_READ (SPI_CMD_SYS_CTRL_ACCESS | SPI_CMD_READ) |
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#define | SPI_CMD_SYS_CTRL_WRITE (SPI_CMD_SYS_CTRL_ACCESS | SPI_CMD_WRITE) |
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#define | SPI_CMD_WRITE (0x4000) |
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#define | SPI_CTRL_IEN_EN_RD (0x0002) |
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#define | SPI_CTRL_IEN_EN_WR (0x0001) |
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#define | SPI_CTRL_RD_FLAG (0x0008) |
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#define | SPI_CTRL_WR_FLAG (0x0004) |
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#define | SYS_CTRL_DEBUG (0x0002) |
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#define | SYS_CTRL_DUMMY_BYTES_BM (0x001C) |
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#define | SYS_CTRL_POR_N (0x0020) |
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#define | SYS_CTRL_RESET_N (0x0001) |
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#define | SYS_CTRL_SCAN_MODE_BM (0x0060) |
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