ch_driver.h

Go to the documentation of this file.

 
/*
 Copyright 2016-2023, InvenSense, Inc.  All rights reserved.
 
 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 DISCLAIMED.
 
 */
 
#ifndef CH_DRIVER_H_
#define CH_DRIVER_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
// #define USE_PRE_PROD_SERIAL_NUM      // if defined, handle pre-production ICU serial number
 
#include <invn/soniclib/soniclib.h>
 
#include <stdint.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <invn/icu_interface/shasta_pmut_instruction.h>
 
#define CHDRV_I2C_MAX_WRITE_BYTES 256 
#define CHDRV_NB_TRANS_TYPE_STD      (0) 
#define CHDRV_NB_TRANS_TYPE_PROG     (1) 
#define CHDRV_NB_TRANS_TYPE_EXTERNAL (2) 
/*** Definitions relative to CHx01 sensors */
 
/* Programming interface register addresses */
#define CH_PROG_REG_PING 0x00 
#define CH_PROG_REG_CPU  0x42 
#define CH_PROG_REG_STAT 0x43 
#define CH_PROG_REG_CTL  0x44 
#define CH_PROG_REG_ADDR 0x05 
#define CH_PROG_REG_CNT  0x07 
#define CH_PROG_REG_DATA 0x06 
#define CH_PROG_ADDR_WDT_REG          (0x0120) 
#define CH_PROG_ADDR_PMUT_CNTRL4_REG  (0x01A6) 
#define CH_PROG_ADDR_DEV_I2C_ADDR_REG (0x01C5) 
#define CH_PROG_ADDR_IDLE_LOC         (CHX01_PROG_MEM_ADDR + CHX01_PROG_MEM_SIZE - 4) 
#define PMUT_CNTRL4_HVVSS_FON (0x0200)
#define PMUT_CNTRL4_HVVDD_FON (0x0400)
 
#define CH_PROG_SIZEOF(R) ((R)&0x40 ? 1 : 2)
#define CH_PROG_XFER_SIZE (256) 
/*** End of definitions relative to CHx01 sensors */
 
#define CHDRV_DEBUG_PIN_NUM (0) 
#define CHDRV_MAX_QUEUE_LENGTH                                                                                         \
    CHIRP_MAX_NUM_SENSORS 
#define CHDRV_FREQLOCK_TIMEOUT_MS                                                                                      \
    100                           
#define CHDRV_BANDWIDTH_INDEX_1 6 
#define CHDRV_BANDWIDTH_INDEX_2                                                                                        \
    (CHDRV_BANDWIDTH_INDEX_1 + 1) 
#define CHDRV_SCALEFACTOR_INDEX 4 
#define CHDRV_TRIGGER_PULSE_US    5   
#define CHDRV_DELAY_OVERHEAD_US   (0) 
#define CHDRV_PRETRIGGER_DELAY_US 600 
#define CHDRV_POST_TRIG_IEN_DELAY_US                                                                                   \
    10 
#define CHDRV_POST_ALGO_INIT_DELAY_MS 3 
#define CHDRV_DELAY_EN_CHARGE_PUMP_MS (5)
#define CHDRV_EVENT_TIMEOUT_MS        (750) 
#define CHDRV_I2C_SPEED_DEFAULT_HZ (400000) 
typedef struct chdrv_transaction {
    uint8_t type;      
    uint8_t rd_wrb;    
    uint8_t xfer_num;  
    uint16_t addr;     
    uint16_t nbytes;   
    ch_dev_t *dev_ptr; 
    uint8_t *databuf;  
} chdrv_transaction_t;
 
typedef struct chdrv_queue {
    uint8_t read_pending; 
    uint8_t running;      
    uint8_t len;          
    uint8_t idx;          
    chdrv_transaction_t transaction[CHDRV_MAX_QUEUE_LENGTH]; 
} chdrv_queue_t;
 
void chdrv_group_measure_rtc(ch_group_t *grp_ptr);
 
void chdrv_group_measure_rtc_no_pulse(ch_group_t *grp_ptr);
 
uint32_t chdrv_one_way_range(ch_dev_t *dev_ptr, uint16_t tof, uint16_t tof_sf);
 
uint32_t chdrv_round_trip_range(ch_dev_t *dev_ptr, uint16_t tof, uint16_t tof_sf);
 
int chdrv_group_queue(ch_group_t *grp_ptr, ch_dev_t *instance, uint8_t rd_wrb, uint8_t type, uint16_t addr,
                      uint16_t nbytes, uint8_t *data);
 
int chdrv_external_queue(ch_group_t *grp_ptr, ch_dev_t *instance, uint8_t rd_wrb, uint16_t addr, uint16_t nbytes,
                         uint8_t *data);
 
void chdrv_group_start_nb(ch_group_t *grp_ptr);
 
void chdrv_group_irq_handler(ch_group_t *grp_ptr, uint8_t bus_index);
 
#ifdef INCLUDE_WHITNEY_SUPPORT
int chdrv_wait_for_lock(ch_dev_t *dev_ptr, uint16_t timeout_ms);
 
int chdrv_group_wait_for_lock(ch_group_t *grp_ptr);
 
#endif  // INCLUDE_WHITNEY_SUPPORT
 
int chdrv_group_hw_trigger(ch_group_t *grp_ptr);
 
int chdrv_hw_trigger(ch_dev_t *dev_ptr);
 
int chdrv_prog_ping(ch_dev_t *dev_ptr);
 
int chdrv_detect_and_program(ch_dev_t *dev_ptr);
 
int chdrv_group_detect_and_program(ch_group_t *grp_ptr);
 
int chdrv_init(ch_dev_t *dev_ptr, uint8_t i2c_addr, uint8_t io_index, uint8_t bus_index, uint16_t part_number);
 
int chdrv_group_prepare(ch_group_t *grp_ptr);
 
uint8_t chdrv_group_start(ch_group_t *grp_ptr);
 
int chdrv_restart(ch_dev_t *dev_ptr);
 
int chdrv_write_byte(ch_dev_t *dev_ptr, uint16_t mem_addr, uint8_t data);
 
int chdrv_write_word(ch_dev_t *dev_ptr, uint16_t mem_addr, uint16_t data);
 
int chdrv_read_byte(ch_dev_t *dev_ptr, uint16_t mem_addr, uint8_t *data);
 
int chdrv_read_word(ch_dev_t *dev_ptr, uint16_t mem_addr, uint16_t *data);
 
int chdrv_burst_read(ch_dev_t *dev_ptr, uint16_t mem_addr, uint8_t *data, uint16_t len);
 
int chdrv_read_buf_addr(ch_dev_t *dev_ptr);
 
int chdrv_burst_write(ch_dev_t *dev_ptr, uint16_t mem_addr, const uint8_t *data, uint16_t num_bytes);
 
int chdrv_soft_reset(ch_dev_t *dev_ptr);
 
int chdrv_group_hard_reset(ch_group_t *grp_ptr);
 
int chdrv_group_soft_reset(ch_group_t *grp_ptr);
 
int chdrv_set_idle(ch_dev_t *dev_ptr);
 
int chdrv_prog_write(ch_dev_t *dev_ptr, uint8_t reg_addr, uint16_t data);
 
int chdrv_prog_i2c_write(ch_dev_t *dev_ptr, const uint8_t *message, uint16_t len);
 
int chdrv_prog_i2c_read(ch_dev_t *dev_ptr, uint8_t *message, uint16_t len);
 
int chdrv_prog_i2c_read_nb(ch_dev_t *dev_ptr, uint8_t *message, uint16_t len);
 
int chdrv_prog_mem_write(ch_dev_t *dev_ptr, uint16_t addr, const uint8_t *message, uint16_t nbytes);
 
int chdrv_pretrigger_delay_set(ch_group_t *grp_ptr, uint16_t delay_us);
 
uint8_t chdrv_sys_ctrl_read(ch_dev_t *dev_ptr, uint8_t *reg_value_ptr);
 
uint8_t chdrv_sys_ctrl_write(ch_dev_t *dev_ptr, uint8_t reg_value);
 
uint8_t chdrv_dbg_reg_read(ch_dev_t *dev_ptr, uint8_t reg_id, uint16_t *reg_value_ptr);
 
uint8_t chdrv_dbg_reg_write(ch_dev_t *dev_ptr, uint8_t reg_id, uint16_t reg_value);
 
uint8_t chdrv_int_notify(ch_group_t *grp_ptr, uint8_t dev_num);
 
void chdrv_int_callback(ch_group_t *grp_ptr, uint8_t dev_num);
 
void chdrv_int_callback_deferred(ch_group_t *grp_ptr, uint8_t dev_num);
 
#ifdef INCLUDE_SHASTA_SUPPORT
 
uint8_t chdrv_event_trigger(ch_dev_t *dev_ptr, uint16_t event);
 
uint8_t chdrv_event_trigger_and_wait(ch_dev_t *dev_ptr, uint16_t event);
 
uint8_t chdrv_otpmem_read(ch_dev_t *dev_ptr);
 
uint8_t chdrv_otpmem_copy(ch_dev_t *dev_ptr, otp_copy_t *otp_copy_ptr);
 
uint8_t chdrv_algo_init(ch_dev_t *dev_ptr);
 
uint8_t chdrv_algo_info_read(ch_dev_t *dev_ptr, ICU_ALGO_SHASTA_INFO *algo_info_ptr);
 
uint8_t chdrv_algo_cfg_read(ch_dev_t *dev_ptr, void *algo_cfg_ptr);
 
uint8_t chdrv_algo_cfg_write(ch_dev_t *dev_ptr, const void *algo_cfg_ptr);
 
uint8_t chdrv_algo_out_read(ch_dev_t *dev_ptr, void *algo_out_ptr);
 
uint8_t chdrv_algo_state_read(ch_dev_t *dev_ptr, void *algo_state_ptr);
 
uint8_t chdrv_meas_queue_write(ch_dev_t *dev_ptr, measurement_queue_t *q_buf_ptr);
 
uint8_t chdrv_meas_queue_read(ch_dev_t *dev_ptr, measurement_queue_t *q_buf_ptr);
 
#endif
 
void chdrv_trig_assert(ch_dev_t *dev_ptr);
 
void chdrv_trig_deassert(ch_dev_t *dev_ptr);
 
void chdrv_trig_group_assert(ch_group_t *grp_ptr);
 
void chdrv_trig_group_deassert(ch_group_t *grp_ptr);
 
void chdrv_trig_set_dir_out(ch_dev_t *dev_ptr);
 
void chdrv_trig_group_set_dir_out(ch_group_t *grp_ptr);
 
void chdrv_int_group_assert(ch_group_t *grp_ptr);
 
void chdrv_int_group_deassert(ch_group_t *grp_ptr);
 
void chdrv_int_set_dir_in(ch_dev_t *dev_ptr);
 
void chdrv_int_group_set_dir_in(ch_group_t *grp_ptr);
 
void chdrv_int_group_set_dir_out(ch_group_t *grp_ptr);
 
void chdrv_int_interrupt_enable(ch_dev_t *dev_ptr);
 
void chdrv_int_interrupt_disable(ch_dev_t *dev_ptr);
 
void chdrv_int_group_interrupt_enable(ch_group_t *grp_ptr);
 
void chdrv_int_group_interrupt_disable(ch_group_t *grp_ptr);
 
uint32_t chdrv_cpu_freq_calculate(ch_dev_t *dev_ptr);
 
uint32_t chdrv_cpu_freq_adjust(ch_dev_t *dev_ptr, uint32_t pmut_freq);
 
uint8_t chdrv_run_bist(ch_dev_t *dev_ptr);
 
void chdrv_group_measure_pmut(ch_group_t *grp_ptr);
 
uint8_t chdrv_check_reset_state(ch_dev_t *dev_ptr, uint8_t *reset_state);
 
void chdrv_enable_mq_sanitize(ch_dev_t *dev_ptr);
 
void chdrv_disable_mq_sanitize(ch_dev_t *dev_ptr);
 
int16_t chdrv_is_mq_sanitize_enabled(const ch_dev_t *dev_ptr);
 
uint8_t chdrv_adjust_rx_len(volatile pmut_transceiver_inst_t *trx_inst, uint8_t cic_odr, int rx_len, int eof_idx);
 
#ifdef __cplusplus
}
#endif
 
#endif /* CH_DRIVER_H_ */